1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to a substrate using a depletion mode transistor to control the body of an enhancement mode transistor, in order to assure that the snapback voltage is lowered, thus, fulfilling the function of a floating body ESD protection circuit.
2. Description of the Related Art
During the fabrication and post-fabrication processes of integrated circuits such as dynamic random access memory (DRAM) and static random access memory (SRAM), electrostatic discharge is often the primary cause of chip damage. For example, a person walking over carpet in a high relative humidity environment can generate several hundred to several thousand volts of electricity. When the charged body makes contact with the chip, static electricity may discharge causing irreparable damage to the chip. A number of methods have emerged to prevent damage to chips by electrostatic discharge. The conventional method commonly uses hardware to prevent electrostatic discharge. That is to say, an on-chip electrostatic discharge protection circuit is positioned evenly between an internal circuit and each bonding pad, to protect the internal circuit. FIG. 1 is the circuit diagram of a conventional ESD protection circuit. As shown in FIG. 1, an ESD protection circuit is positioned between an I/O pad and an internal circuit. The ESD protection circuit is used to control the current flow through I/O pad to internal pad 12, so that excessively high, positive and negative voltage is effectively discharged and falls within an appropriate range.
The protection circuit described above consists of a PMOS transistor 14 and an NMOS transistor 16. The source and gate of PMOS transistor 14 are coupled to a voltage VDD. The drain of the NMOS transistor 16 is coupled to the drain of PMOS transistor 14, both are coupled to the I/O pad and internal circuit at connecting point 18. The gate and source of NMOS transistor 16 are alternatively coupled to the grounded voltage VSS. In conventional practice, bulk ESD protection circuits like the one shown in FIG. 1, use gated N-P structures or gate PMOS-gate NMOS combinations. Thus, the body (well or substrate) of PMOS transistor 14 and NMOS transistor 16 are coupled to the top of the source and are respectively coupled to voltage Vdd and grounded voltage Vss.
The above structure allows excessively high snap back voltage Vsb. As shown in FIG. 2, only after the voltage has exceeded snap back voltage, are PMOS transistor 14 and NMOS transistor 16 triggered, allowing the gradual return to normal operating voltage Vop. Thus, when snap back voltage is excessively high, the ESD protection circuit is unable to respond quickly, permitting electrostatic discharge to damage the circuit, causing product failure.
Accordingly, one object of the present invention is to provide a floating body ESD protection circuit used to lower the range of snapback voltage, which enables the ESD protection circuit to function more rapidly, protecting the internal circuit from the affects of sudden, excessively high voltage.
The present invention provides a floating body ESD protection circuit positioned between and coupled to an input-output pad and an internal circuit. The floating body protection circuit includes the structure constituted by a p-type depletion mode transistor, an n-type depletion mode transistor, a p-type enhancement mode transistor and an n-type enhancement mode transistor.
The gate of p-type depletion mode transistor is coupled to an I/O pad, the source is coupled to a high voltage. The source is coupled to high voltage. The source and gate of p-type enhancement mode transistor are coupled to a high voltage, the drain is coupled to the I/O pad. The body is coupled to the drain of the n-type depletion mode transistor. The source and gate of the n-type enhancement mode transistor are coupled to a grounded voltage, the drain is coupled to I/O pad 30, and the body is coupled to the drain of the p-type depletion mode transistor.
The drain of the n-type depletion mode transistor is coupled to the body of the p-type enhancement mode transistor. Thus, when the n-type depletion mode transistor is triggered, high voltage is passed to the body of the p-type enhancement mode transistor. Alternatively, when the n-type depletion mode has been triggered, the p-type enhancement mode transistor remains in a floating state. Thus, the range of the snapback voltage can be lowered, enabling the ESD protection circuit to respond sooner.
Similarly, because the drain of the p-type enhancement mode transistor is coupled to the body of the n-type enhancement mode transistor, when the p-type depletion mode transistor is triggered, grounded voltage is passed to the body of the n-type enhancement mode transistor. Alternatively, if the p-type depletion mode transistor has not been triggered, the n-type enhancement mode transistor remains in floating state. Thus, the range of the snapback voltage can be lowered, enabling the ESD protection circuit to function sooner.
The field oxide layer of the n-type and p-type depletion mode transistors use local oxidation (LOCOS) or a shallow trench isolation oxide layer. The n-type depletion mode transistor uses a phosphorus or arsenic ion implantation. The p-type depletion mode transistor can use a boron ion implantation. Additionally, the floating body ESD protection circuit of the present invention can be used on a bulk ESD protection circuit as well as any of the recently developed SOI technologies.
The floating body ESD protection circuit of the present invention can also use a single, p-type depletion mode transistor to control the n-type enhancement mode transistor. In this case, the source the gate and the body of the other p-type enhancement mode transistor are all coupled to a high voltage, to enable operation. Similarly, a single, n-type depletion mode transistor can be used to control the p-type enhancement mode transistor. In this case, the source, the gate and the body of the other n-type enhancement transistor are coupled to the grounded voltage, to enable operation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.